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Renesas Electronics /R7FA6M3AH /GLCDC /GR1_FLM2

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Interpret as GR1_FLM2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BASE

Description

Graphics 1 Frame Buffer Control Register 2

Fields

BASE

Base address for accessing graphics data (frame buffer data)Set the head address in the frame buffer where graphics data is to be stored. GRn_FLM2.BASE[5:0] should be fixed to 0 during 64-byte burst transfer.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data